디지털 시스템 설계는 Verilog로 시스템을 작성하여 layout extraction을 해준 것을 얻는다. 그러나 이번 프로젝트에서는 Verilog로 작성한 것을 Gate level schematic을 통해서 layout을 작성해보는 데에 중점을 두고 진행하였다. 툴을 통해 레이아웃 된 것이 얼마나 집적도가 떨어지는지는 모르지만, 나름대로 손으로
perfect, life is the best.
Its full of magic and beauty...
opportunity and television.
And surprises. Lots of surprises, yeah.
And then theres that stuffthat everybody longs for...
but they only really feel when its gone.
All thatjust kind of hit me. I guess you dontreally see it all that clearly when youre...
you know...alive.
I guess you could say my life onlyreally started about two we
certain theyve been
captured by the guerrillas.
Schaefer looks up, puffing lightly on the cigar.
SCHAEFER
(quietly)
What have you got in mind,
General.
(CONTINUED)
------------------------------------------------------------------------
4
3 CONTINUED: (2) 3
PHILIPS
We figure weve got less than
twenty-four hours to catch
up with them. After that,
theres not much hope. We
want a rescue operati
theyve been
captured by the guerrillas.
Schaefer looks up, puffing lightly on the cigar.
SCHAEFER
(quietly)
What have you got in mind,
General.
(CONTINUED)
------------------------------------------------------------------------
4
3 CONTINUED: (2) 3
PHILIPS
We figure weve got less than
twenty-four hours to catch
up with them. After that,
theres not much hope. We
want a rescue operation
mounted