[디스플레이재료실험] TFT(Thin Film Transistor)

 1  [디스플레이재료실험] TFT(Thin Film Transistor)-1
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 3  [디스플레이재료실험] TFT(Thin Film Transistor)-3
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 5  [디스플레이재료실험] TFT(Thin Film Transistor)-5
 6  [디스플레이재료실험] TFT(Thin Film Transistor)-6
 7  [디스플레이재료실험] TFT(Thin Film Transistor)-7
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[디스플레이재료실험] TFT(Thin Film Transistor)에 대한 자료입니다.
목차
■ Experiment Purpose

■ Experiment Process

Photolithography

○ Cleaning
○ Photoresist(PR) spin coating
○ Soft baking
○ Exposure
○ Developing
○ Hard baking
○ Etching

Doping

○ Piranha treatment (in Piranha solution 20minute)
○ Dopamt spin coating (dopant is phosphorus)
○ Doping process by RTA (O2:N2 partial pressure is 1:4)
○ Removing remained Dopant

Deposition of SiO2

○ Alpha step
○ PECVD

Isolation process

○ Photolithography
○ Wet etching

Source Drain Opening

Metal Deposition

○ Metal deposition
○ PR Patterning
○ Metal patterning

■ Experiment Analysis

○ Threshold Voltage
○ VDS = constant ⇒ ID ― VG Curve ( Logarithm scale )
○ VGS = constant ⇒ ID ― VD Curve

■ References


본문내용

○ PECVD
∙ What is PECVD?
⇒ Radio frequency(RF) is used to induce plasma in the deposition gas.
⇒ This results in a higher deposition rate at relatively low temperatures.
⇒ With the plasma enhanced CVD process is the deposition at temperature around 300℃ allows.
⇒ The temperature will be through encouragement of a plasma with high frequency electric fields triggered.
⇒ The silicon is on the gas SiH2Cl2, of which it is at relatively low temperatures separates.
⇒ With the support of the plasma excitation are the low process temperatures at 300℃ is possible.
⇒ The deposition of SiO2 and silicon nitride Si3N4 at low conformity.
⇒ High growth speed up to 500 nm/min is possible.
∙ Deposit at low temperature because of plasma.
∙ High vacuum and taking long time.
⇒ Increase the temperature up to 250℃ despite of low temperature.


SiO2


N-type
Si
N-type






PECVD
Deposited SiO2 by PECVD




Isolation process

○ Photolithography

PR


SiO2


N-type
Si
N-type






⦁Deposit photoresist on SiO2.




SiO2


N-type
Si
N-type






⦁Expose UV light. The part of unexposed removes because of negative PR.


○ Wet etching



SiO2
N-type
Si
N-type
SiO2





⦁SiO2 that does not have PR is removed by wet etching and also remaining PR is removed by acetone.

Source Drain Opening

○ SiO2 Deposition ( 100nm ) ○ PR(positive) Coating







SiO2


SiO2
N-type
Si
N-type
SiO2











PR




SiO2


SiO2
N-type
Si
N-type
SiO2





참고문헌
• Principles of Electronic Materials and Devices - S.O. Kasap
• Introduction To Microelectronic Fabrication - R.C. Jaeger
• Solid State Electronic Devices - Ben Streetman, Sanjay Banergee
• Semiconductor Manufacturing Technology - Quirk, Michael, 1953-Serda, Julian
• PH Effect at Doped Si Semiconductor Interfaces - 천장호 , 나극환
• http://www.mems-exchange.org/MEMS/processes/
• http://ece.utep.edu
• http://www.semipark.co.kr/semidoc/waferfab/
• http://www.udia.co.kr/rnd/lowtem.html
• http://www.kdia.org/ko/lib/theory02.jsp/ - Korea display industry association